Automatic FPGA-based Hardware Accelerator Design: A Case Study with Image Processing Applications

Authors

DOI:

https://doi.org/10.4108/eai.12-5-2020.164497

Keywords:

FPGA-based design framework, Hardware accelerator, Image processing

Abstract

We present a case study of automatic FPGA-based hardware accelerator design using our proposed framework with the image processing domain. With the framework, the ultimate systems are optimized in both performance and energy consumption. Moreover, using the framework, designers can implement FPGA platforms without manually describing any hardware cores or the interconnect. The systems offer accelerations in execution time compared to traditional general purpose processors and accelerator systems designed manually. We use two applications in the image processing domain as experiments to report our work. Those are Canny edge detection and jpeg converter. The experiments are conducted in both embedded and high-performance computing platforms. Results show that we achieve overall speed-ups by up to 3.15´ and 2.87´ when compared to baseline systems in embedded and high-performance platforms, respectively. Our systems consume less energy than other FPGA-based systems by up to 66.5%.

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Published

12-05-2020

How to Cite

1.
Pham-Quoc C. Automatic FPGA-based Hardware Accelerator Design: A Case Study with Image Processing Applications. EAI Endorsed Trans Context Aware Syst App [Internet]. 2020 May 12 [cited 2024 Apr. 24];7(20):e5. Available from: https://publications.eai.eu/index.php/casa/article/view/1888