Low Power Mixed-Signal SoC Integration and Verification Challenges with Third Party IP Cores





Third party IP, MCU, IOT, EDA tool, SoC, CDC, RDC, DV


IP reuse is all about improving productivity and can result in significantly shrinking the design cycle time especially with configurable third party IP cores. Increasing amount of third party IPs find their way onto today's complex system-on-chip (SoC) designs. Hence it is paramount that designers build a large and expanding knowledge base incorporating lessons learned out of accumulated experience from several of designs containing a broad range of IP blocks into tangible design, verification and test methodology components. These components include checklists, automated IC analysis programs, and processes both internal and collaborative. This knowledge base is usually combined with the experience of the individual IP and EDA vendors to ensure the lowest possible risk to each design. Integrating third party IP core typically involves various challenges. These challenges involve compatibility with power, reset and clock (PRC) schemes, design methods used to achieve system low power goals, integration scalability, and design verification methods to achieve comprehensive entitled coverage. Resolving them requires additional design, integration and verification effort. Design verification (DV) in general could be more challenging, as most third party IPs are verified in isolation agnostic to the context of the system. Ensuring that the third party IP cores as used in the SoC will ultimately meet all requirements is a highly complex task that requires a dedicated, expert team with an explicit focus and responsibility towards this task. This paper outlines design and DV challenges and resolution in integrating third party IPs in today’s high-end ASICs/SoCs.




How to Cite

R. Shankar, P. Mishra, A. Parashar, A. K. Padoor, and L. Balasubramanian, “Low Power Mixed-Signal SoC Integration and Verification Challenges with Third Party IP Cores”, EAI Endorsed Trans Cloud Sys, vol. 5, no. 16, p. e2, Nov. 2019.

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