Random verification Strategy for Microcontroller based Subsystems for faster Convergence

Abstract

A typical microcontroller-based system often includes multiple interfaces with an ability to support clock gating and other low power features. For such a complex subsystem, finding issues in block level interaction, low power flows and architecture requires exhaustive random test framework at subsystem level along with unit level randomization. There is no standard approach for developing random verification environment for such subsystems, thus resulting in increased time for development and maintenance. Debugging issues wherein concurrent traffic from different interfaces is active, is challenging and time consuming. In order to support multiple projects with different configurations there is need for scalable and structured approach which would help in achieving quality verification without affecting time to market. A novel dashboard style architecture proposed in this paper, provides fully scalable solution for subsystem level random verification with improved debug ability and execution efficiency, thus contributing to High Velocity Development Model (HVDM). With this scalable approach for random verification, bring up time for a new IP in a Sub system random verification environment is seen reduced by 60% and time required for achieving tape-in quality coverage is seen reduced by 40%, as compared to the traditional approach. The results published are derived from the improvement seen by implementation of this methodology in a Low Power Sensor Subsystem that was delivered to multiple SoCs, in time with quality.