Design and Analysis of Hybrid GDI-PTL Based Wallace Tree Multipliers for Low-Power DCT Architecture in Image Compression
DOI:
https://doi.org/10.4108/eetiot.10362Keywords:
Hybrid full adder, GDI logic, PTL, Wallace Tree multiplier, 2D-DCT, image compression, Low power, area optimization, delay reductionAbstract
This paper presents a hybrid low-power Wallace Tree multiplier architecture employing Gate Diffusion Input (GDI) and Pass Transistor Logic (PTL) techniques, specifically designed for efficient integration into Discrete Cosine Transform (DCT)-based image compression systems. The proposed design incorporates a novel hybrid full adder that leverages the low-power advantages of GDI and the high-speed characteristics of PTL, resulting in a compact, power-optimized solution. GDI logic is utilized for less-transistor-count realization of sum and carry logic, while PTL enhances XOR computation and signal propagation with minimal delay and area overhead. This hybrid adder is embedded into a Wallace Tree multiplier, which serves as a critical computational block within the 2D-DCT transform engine, commonly used in JPEG image compression. The multiplier's efficient structure significantly reduces the number of logic stages needed for partial product reduction, ensuring high throughput and reduced switching activity. Implemented in 90 nm and 45 nm CMOS technologies, the design achieves notable improvements in power-delay product (PDP), area, and energy efficiency when compared to conventional CMOS or single-style logic designs. Simulation of the design is performed using Cadence EDA spectre simulator, results up to a 10× reduction in power consumption and substantial area savings. These results establish the hybrid GDI-PTL-based Wallace Tree multiplier as a highly suitable solution for real-time and portable image processing applications, including mobile devices, low-power high efficiency video encoders, and energy-constrained embedded systems.
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