Review of Network on Chip Routing Algorithms

Authors

  • Khurshid Ahmad University of Engineering and Technology Peshawar image/svg+xml
  • Muhammad Athar Javed Sethi University of Engineering and Technology Peshawar image/svg+xml

DOI:

https://doi.org/10.4108/eai.23-12-2020.167793

Keywords:

System on Chip, Network on Chip, Routing Algorithm

Abstract

System on chip (SoC) is an integrated circuit in which components are communicating through the bus interconnection system. Network on chip (NoC) is a communication network for a multiprocessor system on chip (MPSoC). In NoC architecture node/ component of MPSOC are communicating through a network. The performance of NoC architecture depends on topology, routing algorithm and switching technique. In this paper, different NoC routing algorithms are review using basic parameters of NoC architecture and also provide some information about these parameters. It is concluded that most of the researchers are interested in design of the NoC routing algorithm, which efficiently transmits data from source to destination. When the routing algorithm is congestion aware, fault-tolerant, deadlock-free and live-lock free, then the latency of algorithm decreases and throughput increases.

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Published

23-12-2020

How to Cite

1.
Ahmad K, Javed Sethi MA. Review of Network on Chip Routing Algorithms. EAI Endorsed Trans Context Aware Syst App [Internet]. 2020 Dec. 23 [cited 2024 Nov. 13];7(22):e5. Available from: https://publications.eai.eu/index.php/casa/article/view/1875