Implementation of NoC on FPGA with Area and Power Optimization

Authors

  • Momil Ijaz University of Engineering and Technology Peshawar image/svg+xml
  • Huma Urooj University of Engineering and Technology Peshawar image/svg+xml
  • Muhammad Athar Javed Sethi University of Engineering and Technology Peshawar image/svg+xml

DOI:

https://doi.org/10.4108/eai.23-5-2019.158953

Keywords:

Network on chip, node, switching, packet, crossbar

Abstract

On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems, size, speed, power and area. The goal of working was to design a usable and researchable general-purpose 2x2 mesh NoC architecture, which is not application specific, and have optimized area and power. Desired NoC was coded and deployed on FPGA Spartan-3 kit in a generic mode, with the efficient area and power utilization than traditional deployments.

Downloads

Published

18-03-2019

How to Cite

1.
Ijaz M, Urooj H, Athar Javed Sethi M. Implementation of NoC on FPGA with Area and Power Optimization. EAI Endorsed Trans Context Aware Syst App [Internet]. 2019 Mar. 18 [cited 2024 Apr. 24];6(16):e5. Available from: https://publications.eai.eu/index.php/casa/article/view/1939