Design and Comparison of SEU Tolerant 10T Memory Cell for Radiation Environment Applications
DOI:
https://doi.org/10.4108/ew.5006Keywords:
Single Event Upset, Memory Chip, CMOS, 10T Memory cellAbstract
Single event upsets (SEUs), which are caused by radiation particles, have emerged as a significant concern in aircraft applications. Soft mistakes, which manifest as corruption of data in memory chips and circuit faults, are mostly produced by SEUs. The utilization of SEUs can have both advantageous and detrimental effects in some critical memory applications. Nevertheless, in adherence to design principles, Radiation-Hardening-By-Design (RHBD) methodologies have been employed to mitigate the impact of soft mistakes in memory. This study presents a novel memory cell design, referred to as a Robust 10T memory cell, which aims to improve dependability in the context of aerospace radiation environments. The proposed design has several advantages, including reduced area, low power consumption, good stability, and a decreased number of transistors. Simulations were conducted using the TSMC 65nm CMO technology, employing the Tanner tool. The parameters of the RHB 10T cell were measured and afterwards compared to those of the 12T memory cell. The findings obtained from the simulation demonstrate that the performance of the 10T memory cell surpasses that of the 12T memory cell.
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Islam A, Hasan M. Single-ended 6T SRAM cell to improve dynamic power dissipation by decreasing activity factor. Mediterr J Electron Commun. 2011;7(1):172-181.
Jung I-S, Kim Y-B, Lombardi F. A novel sort error hardened 10T SRAM cells for low voltage operation. IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). 2012 DOI: https://doi.org/10.1109/MWSCAS.2012.6292120
Lin, Liu, Yue Suge, and Lu Shijin. A four-interleaving HBD SRAM cell based on dual DICE for multiple node collection mitigation. J Semicond. 2015; 36(11): 172-181. DOI: https://doi.org/10.1088/1674-4926/36/11/115007
Amit Namdev and Paresh Rawat. Low Power Consumption in 11T SRAM Design by using CMOS Technology. Int J Eng Trends Technol. 2017; 45(10): 524-530.
Yan, Aibin, et al. Double-node-upset-resilient latch design for nanoscale CMOS technology. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2017; 25(6): 1978-1982. DOI: https://doi.org/10.1109/TVLSI.2017.2655079
Giterman, Robert, Lior Atias, and Adam Teman. Area and energy-efficient complementary dual-modular redundancy dynamic memory for space applications. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2016; 25(2): 502-509. DOI: https://doi.org/10.1109/TVLSI.2016.2603923
Guo, Jing, et al. Novel radiation-hardened-by-design (RHBD) 12T memory cell for aerospace applications in nanoscale CMOS technology. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2017; 25(5): 1593-1600. DOI: https://doi.org/10.1109/TVLSI.2016.2645282
Oh, Tae Woo, et al. Power-gated 9T SRAM cell for low-energy operation. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2016; 25(3): 1183-1187. DOI: https://doi.org/10.1109/TVLSI.2016.2623601
Gupta, Shourya, Kirti Gupta, and Neeta Pandey. A 32-nm subthreshold 7T SRAM bit cell with read assist. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2017; 25(12): 3473-3483. DOI: https://doi.org/10.1109/TVLSI.2017.2746683
Ibe, Eishi, et al. Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule. IEEE Trans Electron Devices. 2010; 57(7): 1527-1538. DOI: https://doi.org/10.1109/TED.2010.2047907
Bentoutou, Y. A real time EDAC system for applications onboard earth observation small satellites. IEEE Trans Aerosp Electron Syst. 2012; 48(1): 648-657. DOI: https://doi.org/10.1109/TAES.2012.6129661
Liu, Shih-Fu, Pedro Reviriego, and Juan Antonio Maestro. Efficient majority logic fault detection with difference-set codes for memory applications. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2010; 20(1): 148-156. DOI: https://doi.org/10.1109/TVLSI.2010.2091432
Qi, Chunhua, et al. A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets. IEEE Trans Device Mater Reliab. 2016; 16(3): 388-395. DOI: https://doi.org/10.1109/TDMR.2016.2593590
Rajaei, Ramin, et al. Design of robust SRAM cells against single-event multiple effects for nanometer technologies. IEEE Trans Device Mater Reliab. 2015; 15(3): 429-436. DOI: https://doi.org/10.1109/TDMR.2015.2456832
Reviriego, Pedro, Salvatore Pontarelli, and Juan Antonio Maestro. Concurrent error detection for orthogonal Latin squares encoders and syndrome computation. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2012; 21(12): 2334-2338. DOI: https://doi.org/10.1109/TVLSI.2012.2230655
CH, Naga Raghuram, Bharat Gupta, and Gaurav Kaushal. Single-Event Multiple Effect Tolerant RHBD14T SRAM Cell Design for Space Applications. IEEE Trans Device Mater Reliab. 2021; 21(1): 48-56. DOI: https://doi.org/10.1109/TDMR.2021.3049215
Lin, Dianpeng, et al. A novel SEU tolerant memory cell for space applications. IEICE Electron Express. 2018; 15-20180656. DOI: https://doi.org/10.1587/elex.15.20180656
Wen, Liang, Yuejun Zhang, and Pengjun Wang. Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2020; 28(8): 1935-1939. DOI: https://doi.org/10.1109/TVLSI.2020.2991755
Prasad, Govind, Bipin Chandra Mandi, and Maifuz Ali. Power optimized SRAM cell with high radiation hardened for aerospace applications. Microelectron J. 2020; 103: 104843. DOI: https://doi.org/10.1016/j.mejo.2020.104843
Li, Tianwen, Hongjin Liu, and Haigang Yang. Design and characterization of SEU hardened circuits for SRAM-based FPGA. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2019; 27(6): 1276-1283. DOI: https://doi.org/10.1109/TVLSI.2019.2892838
Zhao, Qiang, et al. Novel write-enhanced and highly reliable RHPD-12T SRAM cells for space applications. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2020; 28(3): 848-852. DOI: https://doi.org/10.1109/TVLSI.2019.2955865
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