Design and Comparison of SEU Tolerant 10T Memory Cell for Radiation Environment Applications
DOI:
https://doi.org/10.4108/ew.5006Keywords:
Single Event Upset, Memory Chip, CMOS, 10T Memory cellAbstract
Single event upsets (SEUs), which are caused by radiation particles, have emerged as a significant concern in aircraft applications. Soft mistakes, which manifest as corruption of data in memory chips and circuit faults, are mostly produced by SEUs. The utilization of SEUs can have both advantageous and detrimental effects in some critical memory applications. Nevertheless, in adherence to design principles, Radiation-Hardening-By-Design (RHBD) methodologies have been employed to mitigate the impact of soft mistakes in memory. This study presents a novel memory cell design, referred to as a Robust 10T memory cell, which aims to improve dependability in the context of aerospace radiation environments. The proposed design has several advantages, including reduced area, low power consumption, good stability, and a decreased number of transistors. Simulations were conducted using the TSMC 65nm CMO technology, employing the Tanner tool. The parameters of the RHB 10T cell were measured and afterwards compared to those of the 12T memory cell. The findings obtained from the simulation demonstrate that the performance of the 10T memory cell surpasses that of the 12T memory cell.
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