ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit

Kannan Nithin K.V.; Balaji V.R.; Mani V.; V. Priya; S.S. Sivaraju; Duraivel A.N.

doi:10.4108/ew.6035

Authors

Kannan Nithin K.V. Amrita Vishwa Vidyapeetham
Balaji V.R. Sri Krishna College of Engineering and Technology
Mani V. SNS College of Engineering
V. Priya KPR Institute of Engineering and Technology
S.S. Sivaraju RVS College of Engineering and Technology
Duraivel A.N. Kings Engineering College

DOI:

https://doi.org/10.4108/ew.6035

Keywords:

ALU, CMOS, Energy Efficient, VLSI, Arithmetic

Abstract

Low power techniques are becoming more important as portable digital applications expand quickly and demand high speed and low power consumption. The ALU is the most crucial and essential component of a central processing unit, as well as numerous embedded systems and microprocessors. Designing a 32-bit ALU that combines an arithmetic unit and a logical unit is the task at hand. The logic unit will do logic operations AND, OR, XOR, and XNOR with the aid of the recommended CMOS technology, while the arithmetic unit will do the arithmetic operations addition, subtraction, increment, and buffering operation. The arithmetic unit is constructed using the 4x1 MUX, 2x1 MUX, and full adder, and the 4x1 MUX, required logic gates, and 4x1 MUX are employed to create the logical unit. Using Cadence Virtuoso Gpdk 180nm Technology, the results of the simulation of the 32-bit ALU, the ideal delay, and the Power were calculated.

Downloads

Download data is not yet available.

Author Biographies

Balaji V.R., Sri Krishna College of Engineering and Technology

Professor, Department of ECE, Sri Krishna College of Engineering and Technology, Kuniamuthur, Coimbatore.

Mani V., SNS College of Engineering

Assistant Professor, Department of Electrical and Electronics Engineering, SNS College of Engineering, Coimbatore - 641107.

V. Priya, KPR Institute of Engineering and Technology

Assistant Professor (Selection Grade), Department of Computer Science and Engineering, Dr NGP Institute of Technology, Coimbatore.

S.S. Sivaraju, RVS College of Engineering and Technology

Professor, Department of Electrical and Electronics Engineering, RVS College of Engineering and Technology, Tamilnadu, India.

Duraivel A.N., Kings Engineering College

Assistant Professor, Department of Electronics and Communication Engineering, Kings Engineering College, Sriperumbudur, Chennai – 602117.

References

[1] Reddy GS, Rao KK. 32-bit arithmetic and logic unit design with optimized area and less power consumption by using GDI technique. International Journal Of Research In Computer Applications And Robotics. 2015 Apr;3(4):51-66.

[2] Kalamani C, Perumal VK, Kumar MV, Muralidharan J. Design of Power and Delay Efficient Fault Tolerant Adder. In 2023 Third International Conference on Artificial Intelligence and Smart Energy (ICAIS) 2023 Feb 2 (pp. 290-293). IEEE.

[3] Kalamani C, Karthick VA, Anitha S, Kumar KK. Design and implementation of 4 bit multiplier using fault tolerant hybrid full adder. International Journal of Electronics and Communication Engineering. 2017 Nov 1;11(5):618-25.

[4] Liril George,R. Khade Padmaja Bangde. H, “32 bit ALU using Clock Gating and Carry Select Adder”, International Journal Of Innovative Research In Technology, , Vol:2,No:1,2015,pp.205-210.

[5] Pragati Nagdeote, Manisha Waje, “Design Of 64-Bit Arithmetic Logic Unit (Alu) Based on Bsim4 Model Using Tanner”, Vol: 2, No: 10, 2016, pp.06-15.

[6] Surekha G, Madesh G, Kumar MP, Sriramoju H. Design and Implementation of Arithmetic and Logic Unit (ALU). In2023 2nd International Conference on Applied Artificial Intelligence and Computing (ICAAIC) 2023 May 4 (pp. 1530-1536). IEEE.

[7] Shukla V, Singh OP, Mishra GR, Tiwari RK. Design of a 4-bit 2’s complement reversible circuit for arithmetic logic unit applications. InThe International Conference on Communication, Computing and Information Technology (ICCCMIT), Special Issue of International Journal of Computer Applications 2012 (pp. 1-5).

[8] Jose A, Jyothisree KR. 8-bit Arithmetic Logic Unit (ALU) using full swing restored M-GDI technique. InInternational Conference on Communication, Embedded-VLSI Systems for Electric Vehicle (ICCEVE 2023) 2023 Apr 12 (Vol. 2023, pp. 49-53). IET.

[9] Kona VG. Design of Area Efficient 32 Bit Arithmetic and Logic Unit ALU using IPASTA for DSP Processors,Vol.8(6), 2019.

[10] Chatterjee B, Sachdev M. Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2005 Nov;13(11):1296-304.

[11] Tang GM, Takata K, Tanaka M, Fujimaki A, Takagi K, Takagi N. 4-bit bit-slice arithmetic logic unit for 32-bit RSFQ microprocessors. IEEE Transactions on Applied Superconductivity. 2015 Dec 9;26(1):1-6.

[12] Tang GM, Qu PY, Ye XC, Fan DR. Logic design of a 16-bit bit-slice arithmetic logic unit for 32-/64-bit RSFQ microprocessors. IEEE Transactions on Applied Superconductivity. 2018 Jan 31;28(4):1-5.

[13] Jagadeeswar Reddy.G, Siddeswara Reddy. S, Settipalli Sujitha, “An Area Efficient 32 Bit Alu Design Using Reversible Gates”, International Journal of Electrical and Computer Engineering, Vol.6 (3), 2023.