Design and Analysis of Energy Efficient Domino Logic Architectures with Single Electron Transistors in Pull Down Network and Keeper Topology

Abstract

Nanotechnology and VLSI goes hand in hand. Modernization of electronics and communication systems has demanded for compactness of the devices with low power and high speed. Conventionally CMOS logic is preferred due to its low power and its high speed benefits. Researches demand a new logic style that can effectively replace conventional CMOS. Many styles including Domino logic are already gaining attention in this regard. The proposed work introduces Single Electron Transistors (SET) instead of NMOS in Pull Down Network and Keeper transistor of Domino Logic. As SETs are predominant in Nanotechnology, when employed in domino logic circuits as a fusion with normal MOS transistors will contribute effectively in terms of area, power and delay. The parameters are estimated with Cadence 45nm (SET- Spice Model) technology. The proposed domino logic architectures come up with an average of 68% energy efficiency when compared with conventional CMOS circuit and its Domino logic predecessors.