Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA


  • Minh Thuong Nguyen Military Information Technology Institute, Hanoi, Vietnam
  • Xuan Nam Tran Le Quy Don Technical University image/svg+xml
  • Vu Duc Ngo Hanoi University of Science and Technology image/svg+xml
  • Quang-Kien Trinh Le Quy Don Technical University image/svg+xml
  • Duc Thang Nguyen Le Quy Don Technical University image/svg+xml
  • Tien Anh Vu Le Quy Don Technical University image/svg+xml



SDM-MIMO, Sphere Detection, K-best, MIMO, FPGA, Sub-Optimal, Wireless communication


Sphere detector (SD) is an effective signal detection approach for the wireless multiple-input multiple-output (MIMO) system since it can achieve near-optimal performance while reducing significant computational complexity. In this work, we proposed a novel SD architecture that is suitable for implementation on the hardware accelerator. We first perform a statistical analysis to examine the distribution of valid paths in the SD search tree. Using the analysis result, we then proposed an enhanced hybrid SD (EHSD) architecture that achieves quasi-ML performance and high throughput with a reasonable cost in hardware. The fine-grained pipeline designs of 4 × 4 and 8 × 8 MIMO system with 16-QAM modulation delivers throughput of 7.04 Gbps and 14.08 Gbps on the Xilinx Virtex Ultrascale+ FPGA, respectively.


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How to Cite

Nguyen, M. T., Tran, X. N., Ngo, V. D., Trinh, Q.-K., Nguyen, D. T., & Vu, T. A. (2023). Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA. EAI Endorsed Transactions on Industrial Networks and Intelligent Systems, 10(1), e3.