An Efficient Discrete Wavelet Transform Architecture with Low Power and Multiplier-Less Structure for Pervasive Biomedical Image Processing Application

Authors

  • Maram Anantha Guptha Sri Satya Sai University of Technology and Medical Science, Madhya Pradesh, India
  • Surampudi Srinivasa Rao Malla Reddy College of Engineering and Technology, Telangana, India
  • Ravindrakumar Selvaraj Sri Shakthi Institute of Engineering and Technology, Coimbatore, Tamilnadu, India

DOI:

https://doi.org/10.4108/eetpht.v9i1.3176

Keywords:

CMOS, power Efficient, Multiplier-Less, DWT Architecture, FPGA, Lifting based

Abstract

INTRODUCTION: Over the past several years analysis of image has moved from larger system to pervasive portable devices. For example, in pervasive biomedical systems like PACS-Picture achieving and Communication system, computing is the main element. Image processing application for biomedical diagnosis needs efficient and fast algorithms and architecture for their functionality. Future pervasive systems designed for biomedical application should provide computational efficiency and portability. The discrete wavelet transform (DWT) designed in on-chip been used in several applications like data, audio signal processing and machine learning.
OBJECTIVES: The conventional convolution based scheme is easy to implement but occupies more memory , power and delay. The conventional lifting based architecture has multiplier blocks which increase the critical delay. Designing the wavelet transform without multiplier is a effective task especially for the 2-D image analysis. Without multiplier Daubechies wavelet implementation in forward and inverse transforms may find efficient. The objective of the work is on obtaining low power and less delay architecture.
METHODS: The proposed lifting scheme for two dimensional architecture reduces critical path through multiplier less and provides low power, area and high throughput. The proposed multiplier is delay efficient.
RESULTS: The architecture is Multiplier less in the predict and update stage and the implementation carried out in FPGA by the use of Quartus II 9.1 and it is found that there is reduction in consumption of power at approximately 56%. There is reduction in delay due to multiplier less architecture.
CONCLUSION: multiplier less architecture provides less delay and low power. The power observed is in milliwatts and suitable for high speed application due to low critical path delay.

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Published

10-01-2023

How to Cite

1.
Guptha MA, Rao SS, Selvaraj R. An Efficient Discrete Wavelet Transform Architecture with Low Power and Multiplier-Less Structure for Pervasive Biomedical Image Processing Application. EAI Endorsed Trans Perv Health Tech [Internet]. 2023 Jan. 10 [cited 2024 Apr. 20];9:e1. Available from: https://publications.eai.eu/index.php/phat/article/view/3176