Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations

S Usha; M Kanthimathi

doi:10.4108/eetsis.5004

Authors

S Usha Sri Sairam Engineering College
M Kanthimathi Sri Sairam Engineering College

DOI:

https://doi.org/10.4108/eetsis.5004

Keywords:

PPA, Three-Operand Adder, Modular Arithmetic, FPGA

Abstract

Binary Three-operand adder serves as a foundation block used within security and Pseudo Random-Bit Generator (PRBG) systems. Binary Three-operand adder was designed using Carry Save Adder but this consumes more delay. Therefore, a Parallel Prefix Adder (PPA) method can be utilized for faster operation. The canonical types of PPA result in a lesser path delay of approximately O (log2 n). These adders can be designed for 8, 16, 24 or n bits. But this work is focused on developing a 24-bit three-operand adder that takes three 24-bit binary numbers as input and generates a 24-bit sum output and a carry using five different PPA methods The proposed summing circuits are operationalized with Hardware-Description-Language (HDL) using Verilog, and then subjected to synthesis using Field -Programmable Gate- Array (FPGA) Vertex 5. On comparing the proposed adders, it shows that the delay and the size occupied are significantly less in the Sklansky PPA. These faster three-operand adders can be utilized for three-operand multiplication in image processing applications and Internet of Things (IoT) security systems.

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