Efficient LDPC Code Design based on Genetic Algorithm for IoT Applications

Thanh-Loc Nguyen-Van; Tan Do Duy; Thien Huynh-The

doi:10.4108/eetinis.v11i4.5843

Authors

Thanh-Loc Nguyen-Van Ho Chi Minh City University of Technology and Education
Tan Do Duy Ho Chi Minh City University of Technology and Education
Thien Huynh-The Ho Chi Minh City University of Technology and Education

DOI:

https://doi.org/10.4108/eetinis.v11i4.5843

Keywords:

LDPC, genetic algorithm, short block length, Internet of Things

Abstract

In this paper, we propose a low-density parity check (LDPC) code design scheme that improves the performance of the existing genetic algorithm-based LDPC scheme. In particular, we enhance the performance of the LDPC code by removing the girth-4 property of the parity check matrix and utilizing the min-sum decoding algorithm instead of the belief propagation decoding algorithm. In addition, we consider different short block-length scenarios, including 64-bit and 128-bit block length. Then, we evaluate the block error rate (BLER) of the LDPC code over the binary input additive white Gaussian noise (BI-AWGN) channel. Finally, extensive simulation results indicate that our proposed approach achieves more than 11% gain in terms of BLER compared with the benchmarked schemes.

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References

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