Energy-Efficient Lightweight Edge Inference via MOSI-AirComp: Over-the-Air Convolution and Communication-Aware Dual-Branch Training
DOI:
https://doi.org/10.4108/eetsis.12310Abstract
Lightweight, energy-efficient edge intelligence underpins next-generation pattern recognition for IoT and wireless edge computing. Over-the-air computing (AirComp) is a promising communication-computation integration paradigm, yet its distributed inference deployment is severely hindered by signal phase misalignment and channel-induced performance degradation. This paper proposes a lightweight energy-efficient edge inference framework based on the novel Multiple-Output Single-Input AirComp (MOSI-AirComp) architecture, which inherently eliminates the phase alignment issue of traditional AirComp systems. A communication-aware dual-branch training strategy is introduced to boost robustness against wireless channel impairments without compromising inference efficiency, incorporating channel fading and noise in training while keeping inference model complexity unchanged for adaptive recognition in dynamic edge environments. Additionally, a weight-aware power control scheme enables over-the-air convolution, executing multiply–accumulate operations via wireless signal superposition. An improved TSP-based node selection and resource scheduling algorithm, considering model weights and path loss, achieves a desirable energy-accuracy trade-off for collaborative edge inference. Extensive simulations on MNIST/CIFAR-10 with LeNet-5/VGGNet-16 show the framework significantly improves inference accuracy and MSE performance under various SNRs and power constraints, while reducing edge device latency and computational load, providing an effective solution for lightweight energy-efficient pattern recognition in edge intelligence systems. The proposed design also provides quantization-friendly lightweight benefits: CNN weights and intermediate features can be mapped to bounded antenna-level power-control factors and low-bit transmitted amplitudes, thereby reducing high-precision multiply-accumulate operations, memory access, latency, and energy consumption on resource-constrained edge devices.
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